1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having a single bit line structure.
2. Discussion of the Related Art
A conventional SRAM having a single bit line structure will be described with reference to FIG. 1.
FIG. 1 is a schematic circuit of a conventional SRAM having a single bit line structure.
As shown in FIG. 1, the conventional SRAM includes a plurality of bit lines BL.sub.O -BL.sub.N formed in one direction, a plurality of word lines WL.sub.O -W.sub.N formed to cross the bit lines respectively, a plurality of memory cells formed on crossing points of the respective bit lines and the respective word lines, and a plurality of sensing amplifiers SA.sub.O -SA.sub.N for sensing data stored in the corresponding memory cell, through the respective bit lines.
If a high signal is applied to any word line, the memory cell connected to the word line is turned on so that data stored therein is output through the corresponding bit line. The data output from the memory cell is sensed to data 0 or 1 by the sensing amplifier connected to the corresponding bit line.
Generally, a multi-port SRAM includes a plurality of bit lines per one cell. If only a single bit line is used in such a multi-port SRAM, unstable data sensing is performed.
A conventional memory will be described with reference to the accompanying drawings.
FIG. 2 is a detailed schematic view of a conventional semiconductor memory.
As shown in FIG. 2, the conventional memory includes a bit line BL, a bit bar line BL, a bit line pull-up transistor 21 connected to one side of the bit line, a bit bar line pull-up transistor 21a connected to one side of the bit bar line BL, a memory cell connected to the bit line, and a sensing amplifier 25 for sensing data applied to the bit line BL and the bit bar line BL after equalizing the data.
The pull-up transistors 21 and 21a include a first transistor Q1 of which a gate and a source are connected to a power source voltage terminal Vcc, a second transistor Q2 of which a gate is connected to a signal applied to a cell plate and a drain is connected to a drain of the first transistor Q1, and a third transistor Q3 of which a gate is connected to the power source voltage terminal Vcc and a drain is connected to the drain of the second transistor Q2.
A fourth transistor Q4 is connected to the front end of the sensing amplifier 25, which equalizes the data applied to the bit line and the bit bar line.
The sensing amplifier 25 serves as a differential sensing amplifier, of which one terminal is connected to a drain of the fourth transistor Q4 and the other terminal is connected to a source thereof.
In the aforementioned conventional semiconductor memory, if the first transistor Q1 is turned on, "A" point is precharged at level of V.sub.CC -V.sub.th. At this time, if the cell plate is selected, the second transistor Q2 is turned on so that the bit line is precharged at level of V.sub.CC -V.sub.th -.DELTA.V. Since potentials of the bit line BL and the bit bar line BL are equalized by the fourth transistor Q4, the bit line is actually precharged at level (V.sub.CC -V.sub.th -.DELTA.V)/2. Precharge level of the bit line serves as a reference level.
If a word line for reading is selected and a high signal is applied, the precharge level of the bit line is varied as follows.
That is to say, if the memory cell is high when a high signal is applied to the word line shown in FIG. 2, the precharge level of the bit line is maintained at (V.sub.CC -V.sub.th -.DELTA.V)/2+.DELTA.V.sub.1. While, if the memory cell is low, the precharge level of the bit line is maintained at (V.sub.CC -V.sub.th -.DELTA.V)/2-.DELTA.V.sub.1.
In data sensing using the conventional semiconductor memory, since the sensing amplifier serves as a differential sensing amplifier, high level of the bit line has a value of (V.sub.CC -V.sub.th -.DELTA.V)/2+.DELTA.V.sub.1 and the reference level has a value of (V.sub.CC -V.sub.th -.DELTA.V)/2, so that voltage swing of the bit line becomes .DELTA.V.sub.1 substantially. Likewise, since low level of the bit line has a value of (V.sub.CC -V.sub.th -.DELTA.V)/2-.DELTA.V.sub.1, voltage swing of the bit line becomes .DELTA.V.sub.1, substantially.
FIG. 3 is a graph illustrating voltage swing of the bit line according to the conventional semiconductor memory.
As shown in FIG. 3, if the cell plate is selected and a high signal is applied to the word line WL, the precharge level of the bit line becomes (V.sub.CC -V.sub.th -.DELTA.V)/2. At this time, if the memory cell 23 is high, the precharge level of the bit line is maintained at (V.sub.CC -V.sub.th -.DELTA.V)/2+.DELTA.V.sub.1. While if the memory cell 23 is low, the precharge level of the bit line is maintained at (V.sub.CC -V.sub.th -.DELTA.V)/2.DELTA.V.sub.1. Therefore, since the precharge level of the bit line serves as a reference level when the cell plate is selected and a high signal is applied to the word line, voltage difference between the reference level and the precharge level depending on the memory cell becomes .DELTA.V.sub.1.
However, the conventional semiconductor memory has several problems.
Since the bit line of .DELTA.V.sub.1 has half swing, it is more unstable than full swing of the double bit line. This results in wrong data sensing in the case that the bit line is affected by noise.